Minimum qualifications:

• Bachelor's degree in Electrical Engineering or related technical field, or equivalent practical experience.
  
• 5 years of experience in Physical Implementation of High Performance ASICs.
  
• Experience building ASIC implementation flows (RTL-to-GDS2).
  

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering or related technical field.
  
• Experience as technology lead driving Physical Implementation for complex ASIC project(s).
  
• Experience with pre-silicon and post-silicon Design For Test (DFT).
  
• Experience in sign-off convergence including Static timing analysis (STA), electrical checks, and physical verification.
  
• Experience in package design and signal/power integrity (SI/PI) analysis and strategies.
  
• Experience in guiding external vendors in RTL-to-GDS2 chip execution.
  

About the job

In this role, you will be a vital member of the quantum electronics team, providing technical leadership in the area of Application Specific Integrated Circuit (ASIC) physical design as we realize sophisticated electronics for control and readout of our future quantum computers. You will work as part of a team of digital designers and RF/analog/mixed-signal engineers, collaborating with adjacent teams in the electronic, software, and quantum engineering areas to implement complex ASICs for use in the readout and control of our scaled quantum processors.

The US base salary range for this full-time position is $177,000-$266,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

• Manage the development and maintenance of an industry-standard ASIC implementation flow and use it to perform RTL-to-GDS2 digital physical implementation, including synthesis, floor planning, place and route, Clock Tree Synthesis (CTS), Design For Test (DFT) (Scan, MBIST, BISR), Static Timing Analysis (STA), signal/power integrity (SI/PI), Layout Versus Schematic and Design Rule Checking (LVS/DRC).
  
• Develop an understanding of RTL and functionality from a full chip perspective, collaborate with RTL design and architecture. Develop and own full chip timing constraints.
  
• Perform intellectual Property (IP) evaluation and engagement with Computer-aided design (CAD) vendors. 
  
• Drive physical design schedule working with internal front end team and ASIC vendor.
  
• Interface with ASIC vendors, participate in Statement of Work generation, and own the physical implementation signoff, ensuring vendor Physical Implementation meets requirements. Own the RTL/netlist handoff to vendor including quality checks.