Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  
• 3 years of experience with digital logic design principles, RTL design concepts, and languages such as Verilog or SystemVerilog.
  
• Experience with logic synthesis techniques to optimize RTL code, performance and power as well as low-power design techniques.
  
• Experience working with microarchitecture or design of high-performance designs.
  

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  
• Experience with computer architecture or memory subsystem architecture.
  
• Experience working with power, performance, and area trade-offs.
  
• Experience with accelerators (Machine Learning or GPUs) or similar high-performance designs.
  

About the job

Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

In this role, you will architect, design, and verify digital logic using Chisel, Verilog or SystemVerilog for the gChips Tensor Processing Unit (TPU) team. You will interface with architects to define features and interface with Physical Design teams to ensure efficient implementation to produce high-quality Power Performance Area (PPA). You will work with Production and Silicon Validation teams to enable chip bring-up and production tests.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

The US base salary range for this full-time position is $127,000-$187,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

• Oversee the architecture, design and implementation of digital logic using Chisel, Verilog or SystemVerilog.
  
• Engage with Machine Learning System Architects and Software teams to define specifications.
  
• Engage with Verification and Silicon Validation teams to ensure functionality of the design.
  
• Provide input on synthesis, timing closure, and Physical Design of digital blocks.
  
• Perform power, area and performance trade-offs of digital designs and architectures.