Job Title: Sr. Staff Engineer - Machine Learning (MLA) Verification
Job Location: San Jose, CA
Job ID: AI2309
Job Description:
The MLA Design Verification (DV) team at SiMa is involved in the functional verification of Machine Learning Accelerator (MLA) and computer vision pipeline at block, sub-system and SoC level. Will also be involved in bringup and debug on emulator. Responsibilities: As the MLA Design Verification Engineer, you will
- Participate in MLA architecture, micro-architecture and feature discussions and reviews
- Define and develop MLA test bench components using UVM & SystemVerilog
- Develop DV reference models as needed in C or SystemVerilog
- Develop and execute a test plan
- Verification execution of MLA and MLSoC functionality and performance measurements
- Manage debug test and regression failures, as well emulation failures
Requirements:
- BS/MS in EE (Electrical Engineering) or CS (Computer Science) with 8+ years of experience in functional verification of pipe-line based design preferably MLAs, DSPs, CPUs or GPUs
- Very good experience of UVM and SystemVerilog based verification methodology is a must
- Proficiency in C/C++ programming is a plus
- Working experience on emulation is a plus
- Good debug and problem solving skill
Personal attributes:
Can-do attitude. Strong team player. Curious, creative and good at solving problems. Execution and results-oriented. Self-driven, Thinks Big and is highly accountable. Good communication skills.
The annual salary for this position ranges from $180,000 - $238,000. The actual annual salary paid for this position will be based on several factors, including but not limited to, skills, prior experiences, qualifications, expertise, work location, total target compensation, training, company needs, and current market demands. The annual salary range for this position is subject to change and may be adjusted in the future.
