d-Matrix has fundamentally changed the physics of memory-compute integration with our digital in-memory compute (DIMC) engine. The “holy grail” of AI compute has been to break through the memory wall to minimize data movements. We’ve achieved this with a first-of-its-kind DIMC engine. Having secured over $154M, $110M in our Series B offering, d-Matrix is poised to advance Large Language Models to scale Generative inference acceleration with our chiplets and In-Memory compute approach. We are on track to deliver our first commercial product in 2024. We are poised to meet the energy and performance demands of these Large Language Models. The company has 100+ employees across Silicon Valley, Sydney and Bengaluru.

Our pedigree comes from companies like Microsoft, Broadcom, Inphi, Intel, Texas Instruments, Lucent, MIPS and Wave Computing. Our past successes include building chips for all the cloud hyperscalers globally - Amazon, Facebook, Google, Microsoft, Alibaba, Tencent along with enterprise and mobile operators like China Mobile, Cisco, Nokia, Ciena, Reliance Jio, Verizon, AT&AT. We are recognized leaders in the mixed signal, DSP connectivity space, now applying our skills to next generation AI.  

Location:

Hybrid, working onsite at our Santa Clara, CA headquarters 3 days per week

Job Description: Signal and Power integrity Engineer, Staff

What You Will Have:

· Develop next generation chiplet D2D and memory interfaces with SI/PI focus

· Develop and implement SI/PI design guidelines and best practices to ensure signal integrity and power delivery in packages and PCBs

· Power distribution network IR drop and noise evaluation as well as optimization in packages and PCBs

· System-level signal integrity simulation of high speed links such as PCIE, Ethernet, LPDDR and DDR

· Analyze and optimize Power delivery network (PDN) on PCBs and Packages.

· TDR & VNA measurement for PKG/PCB material characterization and model correlation

· Analyze measured data to validate simulation results and identify areas for improvement

· Present SI analysis results, guidelines, and recommendations to stakeholders in a clear and actionable manner

What You Will Bring:

· PhD or Master’s in electrical engineering or a related field.

· Minimum 5 years of experience in SI/PI analysis and design.

· Strong understanding of high-speed SERDES and D2D link architectures

· Knowledge of electromagnetic field theory and transmission line theory

· Proficiency in 3D EM simulation tools such as Ansys HFSS, Cadence Clarity, or equivalent

· Experience with Chiplets, 2.5D/3D package development is highly desired

· Experience with package BGA ball assignments with SI/PI tradeoffs

· Experience with Chip Package Board co-designs

· Proficiency with Oscilloscope, VNA and TDR measurements

· Proficiency with simulation tools such as ADS, HSPICE and other equivalent tools

· Excellent problem-solving and analytical skills.

· Strong communication and interpersonal skills.

· Ability to work independently and as part of a team.

Equal Opportunity Employment Policy

d-Matrix is proud to be an equal opportunity workplace and affirmative action employer. We’re committed to fostering an inclusive environment where everyone feels welcomed and empowered to do their best work. We hire the best talent for our teams, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. Our focus is on hiring teammates with humble expertise, kindness, dedication and a willingness to embrace challenges and learn together every day.

d-Matrix does not accept resumes or candidate submissions from external agencies. We appreciate the interest and effort of recruitment firms, but we kindly request that individual interested in opportunities with d-Matrix apply directly through our official channels. This approach allows us to streamline our hiring processes and maintain a consistent and fair evaluation of al applicants. Thank you for your understanding and cooperation.