Minimum qualifications:

• PhD degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• Experience with Signal and Power Integrity (SI/PI) fundamental concepts, microwave theory, or analog circuit design.

Preferred qualifications:

• Experience in AMS (Analog Mixed Signal) design.
• Experience in Matlab, Python, C++ to establish automation flows and data processing.
• Experience with Signal and Power Integrity (SI/PI) analysis and design for high-speed digital systems, including chip-package co-design concepts.
• Experience with SIPI or microwave modeling tool chains (e.g., HFSS, ADS, Sigrity, Siwave, etc).
• Excellent programming and data analysis skills.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As a Signal Integrity/Power Integrity Engineer, you will lead chip and package design, ensuring optimal SI/PI performance and system co-design from concept to production. You will collaborate within a cross-functional team, including Chip Design, IP, System Design, Software, and Vendors. You will drive signal and power design implementations on chip and advanced packages.

The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world.

We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud’s Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.

The US base salary range for this full-time position is $132,000-$189,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google. Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

• Be responsible for driving chip-package-system co-design by performing SI/PI analysis and optimization to involve in the product definition and optimize chip floorplan, power tree structure, net lists, etc for High Performance Computing (HPC) based on 2.5D/3D package technology.
• Collaborate with chip design team, system design teams and suppliers to drive chip package SI/PI design goal, define boundaries of chip design and explore SI/PI and Design for Manufacturing (DFM) trade-off for package design closure for production.
• Provide feedback on chip floorplan considering package/system routability and SI/PI.
• Develop methodology to enhance accuracy and productivity.
• Support workflows for post-silicon validation, qualification of high speed interface for New Product Introduction (NPI), high speed Interface IP evaluation (serdes, memory), and high power, large DI/DT power integrity.