d-Matrix has fundamentally changed the physics of memory-compute integration with our digital in-memory compute (DIMC) engine. The “holy grail” of AI compute has been to break through the memory wall to minimize data movements. We’ve achieved this with a first-of-its-kind DIMC engine. Having secured over $154M, $110M in our Series B offering, d-Matrix is poised to advance Large Language Models to scale Generative inference acceleration with our chiplets and In-Memory compute approach. We are on track to deliver our first commercial product in 2024. We are poised to meet the energy and performance demands of these Large Language Models. The company has 100+ employees across Silicon Valley, Sydney and Bengaluru.

Our pedigree comes from companies like Microsoft, Broadcom, Inphi, Intel, Texas Instruments, Lucent, MIPS and Wave Computing. Our past successes include building chips for all the cloud hyperscalers globally - Amazon, Facebook, Google, Microsoft, Alibaba, Tencent along with enterprise and mobile operators like China Mobile, Cisco, Nokia, Ciena, Reliance Jio, Verizon, AT&AT. We are recognized leaders in the mixed signal, DSP connectivity space, now applying our skills to next generation AI.  

Location:

Hybrid, working onsite at our Santa Clara, CA headquarters 3 days per week.

The role: RTL Digital Design Engineer, Principal

What you will do:

• Be responsible for the micro-architecture and design of the High-speed IO interfaces.

• Lead the design and implementation of high-performance PCIe Gen5 and beyond interface modules, ensuring compatibility with industry standards and seamless integration into overall system architecture.

• Own design, document, execute and deliver fully verified, high performance, area and power efficient RTL to achieve the design targets and specifications.

• Design of micro-architecture and RTL, synthesis, logic and timing verification using leading edge CAD tools and semiconductor process technologies.

• Design and Implement logic functions that enable efficient test and debug.

• Participate in silicon bring-up and validation for blocks owned.

What you will bring:

Minimum:

• BSEE 8+ years of meaningful work experience / Master’s degree preferred in electrical engineering, Computer Engineering or Computer Science with 5 years of meaningful work experience.

• Experience in micro-architecture and RTL development (Verilog/System Verilog), focused on Processor, Digital Signal Processing blocks.

• Exposure to Mixed-signal designs, Computer Architecture & Arithmetic is required.

• Good understanding of ASIC design flow including RTL design, verification, logic synthesis and timing analysis.

• Strong interpersonal skills and an excellent teammate.

#LI-BP1

Equal Opportunity Employment Policy

d-Matrix is proud to be an equal opportunity workplace and affirmative action employer. We’re committed to fostering an inclusive environment where everyone feels welcomed and empowered to do their best work. We hire the best talent for our teams, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. Our focus is on hiring teammates with humble expertise, kindness, dedication and a willingness to embrace challenges and learn together every day.

d-Matrix does not accept resumes or candidate submissions from external agencies. We appreciate the interest and effort of recruitment firms, but we kindly request that individual interested in opportunities with d-Matrix apply directly through our official channels. This approach allows us to streamline our hiring processes and maintain a consistent and fair evaluation of al applicants. Thank you for your understanding and cooperation.